The present invention relates to the manufacture of substrates. More particularly, the invention provides a technique including a method and device for treating a first substrate to a second substrate for the manufacture of semiconductor integrated circuits, for example. But it will be recognized that the invention has a wider range of applicability; it can also be applied to other substrates for multi-layered integrated circuit devices, three-dimensional packaging of integrated semiconductor devices, photonic devices, piezoelectronic devices, microelectromechanical systems (“MEMS”), sensors, actuators, solar cells, flat panel displays (e.g., LCD, AMLCD), biological and biomedical devices, and the like.
Integrated circuits are fabricated on chips of semiconductor material. These integrated circuits often contain thousands, or even millions, of transistors and other devices. In particular, it is desirable to put as many transistors as possible within a given area of semiconductor because more transistors typically provide greater functionality, and a smaller chip means more chips per wafer and lower costs.
Some integrated circuits are fabricated on a slice or wafer, of single-crystal (i.e., monocrystalline) silicon, commonly termed a “bulk” silicon wafer. Devices on such a “bulk” silicon wafer typically are isolated from each other. A variety of techniques have been proposed or used to isolate these devices from each other on the bulk silicon wafer, such as a local oxidation of silicon (“LOCOS”) process, trench isolation, and others. These techniques, however, are not free from limitations. For example, conventional isolation techniques consume a considerable amount of valuable wafer surface area on the chip, and often generate a non-planar surface as an artifact of the isolation process. Either or both of these considerations generally limit the degree of integration achievable in a given chip. Additionally, trench isolation often requires a process of reactive ion etching, which is extremely time consuming and can be difficult to achieve accurately. Bulk silicon wafers, which are greater than 200 millimeters, are not free from defects and can reduce overall devices yields and the like.
An approach to achieving very-large scale integration (“VLSI”) or ultra-large scale integration (“ULSI”) uses epitaxial silicon wafers, which are commonly known as “epi-wafers.” Epi-wafers often have a layer of high quality single crystalline silicon material defined overlying a face of a bulk substrate. The high quality silicon layer provides a good site for fabricating devices, often with higher yields, than conventional bulk silicon wafer materials. The high quality silicon material is often deposited by way of epitaxial silicon process reactors made by companies called Applied Materials, Inc. of Santa Clara, Calif. or ASM of Phoenix, Ariz.
Epitaxial wafers offer other advantages over bulk silicon technologies as well. For example, epitaxial wafers have almost perfect crystalline characteristics, which enhance device speed, functionality, and reliability. Additionally, the epitaxial wafers often provide higher device yields, than conventional bulk wafers. Many problems, however, than have already been solved regarding fabricating devices on bulk silicon wafers remain to be solved for fabricating devices on epitaxial silicon wafers. Epitaxial silicon wafers are made by way of epitaxial reactors, which are often expensive to purchase and difficult to maintain. The process of forming epitaxial silicon is also slow and time consuming. Accordingly, resulting epitaxial silicon wafers can often be expensive and cannot be used for the manufacture of many commercial or commodity devices such as dynamic random access memory devices (i.e., DRAMs), for example.
Another approach to achieving large scale integration often uses bonding substrates made of silicon bearing materials. Such bonding wafers are often made using layer transfer techniques and plasma activated bonding processes. An example of such a plasma activated process is described in U.S. Pat. No. 6,645,828, in the names of Farrens, et al., which issued Nov. 11, 2003, and is commonly assigned to Silicon Genesis Corporation of San Jose, Calif. The Farrens, et al. patent relates generally to in-situ plasma activated bonding techniques. These techniques have become important for the manufacture of bonding semiconductor substrates. Although Farrens, et al. has been effective, there may still be a need for improved bonding techniques.
From the above, it is seen that an improved technique for manufacturing a multi-layered wafer is highly desirable.